LTC4257CS8【PDF 10/20 页】IC CTRLR INTFACE PWR/ETHER 8SOIC

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LTC4257

4257fb

is designed to accept this thermal load and is thermally

protected to avoid damage to the onboard power MOSFET.

Note that the PD designer must ensure that the PD steady-

state power consumption falls within the limits shown in

Table 2.

Power Good

The LTC4257 includes a power good circuit (Figure 6) that

is used to indicate to the PD circuitry that load capacitor C1

is fully charged and that the PD can start DC/DC converter

operation. The power good circuit monitors the voltage

across the internal power MOSFET and PWRGD is as-

serted when the voltage drops below 1.5V. The power

good circuit includes a large amount of hysteresis to allow

the LTC4257 to operate near the current limit point without

inadvertently disabling PWRGD. The MOSFET voltage

must increase to 3V before PWRGD is disabled.

If a sudden increase in voltage appears on the input line,

this voltage step will be transferred through capacitor C1

and appear across the power MOSFET. The response of

the LTC4257 will depend on the magnitude of the voltage

step, the rise time of the step, the value of capacitor C1 and

the DC load. For fast rising inputs, the LTC4257 will

attempt to quickly charge capacitor C1 using an internal

secondary current limit circuit. In this scenario, the PSE

current limit should provide the overall limit for the circuit.

For slower rising inputs, the 350mA current limit in the

LTC4257 will set the charge rate of capacitor C1. In either

case, the PWRGD signal may go inactive briefly while the

capacitor is charged up to the new line voltage. In the

design of a PD, it is necessary to determine if a step in the

input voltage will cause the PWRGD signal to go inactive

and how to respond to this event. In some designs, the

charge on C1 is sufficient to power the PD through this

event. In this case, it may be desirable to filter the PWRGD

signal so that intermittent power bad conditions are

ignored. Figure 10 demonstrates methods to insert a

lowpass filter on the power good interface.

For PD designs that use a large load capacitor and also

consume a lot of power, it is important to delay activation

of the PD circuitry with the PWRGD signal. If the PD cir-

cuitry is not disabled during the current-limited turn-on se-

quence, the PD circuitry will rob current intended for charg-

ing up the load capacitor and create a slow rising input,

possibly causing the LTC4257 to go into thermal shutdown.

The PWRGD pin connects to an internal open-drain, 100V

transistor capable of sinking 1mA. Low impedance indi-

cates power is good. PWRGD is high impedance during

signature and classification probing and in the event of a

thermal overload.

During turn-off, PWRGD is deactivated when the input

voltage drops below 30V. In addition, PWRGD may go

active briefly at turn-on for fast rising input waveforms.

PWRGD is referenced to the V

pin and when active will

be near the V

potential. The PD DC/DC converter will

typically be referenced to V

OUT

and care must be taken to

ensure that the difference in potential of the PWRGD signal

does not cause any detrimental effects. Use of diode clamp

D6, as shown in Figure 10, will alleviate any problems.

Figure 6. LTC4257 Power Good

APPLICATIO S I FOR ATIO

PWRGD

5礔

MIN

OUT

1.125V

100k

300k

LTC4257

THERMAL SHUTDOWN

UVLO

4257 F06

PSE

LOAD

SHDN

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